1. Field of the Invention
The present invention relates to an area mount type semiconductor device, and a die bonding resin composition and encapsulating resin composition used for the same.
2. Description of the Related Art
As the electronic instruments are recently having smaller sizes and lighter weights and exhibiting higher functions in market, semiconductors (hereinafter it may be referred as an integrated circuit (IC)) are more highly integrated and surface mounting of semiconductor devices (hereinafter it may be referred as a package) is promoted. An area mount type semiconductor device is developed as a novel form of package and preference of semiconductor devices is shifting from the semiconductor device of a conventional structure to the area mount type semiconductor device. Specifically, as representative area mount type semiconductor devices, there may be the ball grid array (hereinafter referred as BGA), and the chip scale package (hereinafter referred as CSP), which has smaller size than the BGA. They are proposed so as to meet demand of the package having a greater number of pins and higher speed, of which the conventional surface mounting type semiconductor devices represented by the quad flat package (hereinafter referred as QFP) and the small outline package (SOP) are approaching the limit since the mounting method of the conventional surface mounting type semiconductor device has the electrode arrangement as a surrounding structure of an IC, thus, the electrode can only be taken from around the IC.
The area mount type semiconductor device has a structure that a semiconductor element is mounted on one surface of a substrate such as a rigid circuit board as typified by a bismaleimide triazine (hereinafter referred as BT) resin/copper foil circuit board or a flexible circuit board as typified by a polyimide resin film/copper foil circuit board, and the element mounted surface, that is, only one surface of the circuit board is molded and encapsulated with the use of a resin composition or the like. On the other surface of the element mounted surface of the board, solder balls are formed in parallel in a gird pattern or a peripheral pattern so that when the semiconductor device is mounted on a circuit board for the semiconductor device, the surface having the solder balls formed and the circuit board are bonded. The electrode arrangement of such a mounting method is a matrix structure, thus, the area having the IC mounted can be utilized to take the electrode, which is advantageous for increasing number of in-put/out-put terminal and downsizing. As the structure of the area mount type semiconductor device, a structure using a metal substrate such as a lead frame or the like as the substrate to mount the semiconductor element is also invented besides the above-mentioned organic circuit boards.
As mentioned above, the area mount type semiconductor device has a structure of “one surface encapsulating form”, wherein only the element mounted surface of the board is encapsulated with the use of a resin composition without encapsulating the solder ball formed surface. Only occasionally, the metal substrate such as the lead frame or the like may have an encapsulating resin layer of about several tens of μm on the solder ball formed surface. However, since an encapsulating resin layer having about several hundreds of μm to several mm is formed on the element mounted surface, the metal substrate substantially has a “one surface encapsulating form”. When only one surface is encapsulated, due to the inconsistency of thermal expansion and thermal shrinkage between the organic substrate or metal substrate and the cured product of the resin composition, or the curing shrinkage upon molding and curing of the resin composition, warpage is likely to be caused in the semiconductor device right after molding. Also, upon performing the solder bonding on the circuit board for mounting the semiconductor device, crack is caused in the semiconductor device due to the stress which is generated when the semiconductor device, wherein moisture in present in the semiconductor device as the cured product of resin composition of the semiconductor device absorbs moisture, is subjected to a high temperature environment during a solder reflow treatment and the moisture quickly evaporates.
In order to solve the problems, an encapsulant using a resin excellent in heat resistance and adhesion (for instance, see Japanese Patent Application Laid-open (JP-A) No. 2000-302, 842, p. 2-6), and a die bonding material having increased adhesion strength (for instance, see JP-A No. 2001-123, 013, p. 2-8) are studied. However, a lead-free solder having higher melting point than a conventional solder is increasingly used from the viewpoint of the environmental concerns. By applying the lead-free solder, mounting temperature needs to be increased by about 20° C. than that of the conventional solder. Hence, there is a problem that reliability of the semiconductor device after mounting decreases significantly than current situation. Therefore, demand for improvement in the resin composition so as to improve reliability of the semiconductor device is increasing. Development of a semiconductor device excellent in reflow crack resistance is desired.
Furthermore, recently, a semiconductor device (package) having elements of different functions or the like mounted on the same device is developed to pursue higher function of the semiconductor device. As such a package, there is a stacked package (hereafter it may be also referred as “area mount type semiconductor device mounting a stacked element”). The stacked package is a package wherein plural semiconductor elements of different functions, for instance, a logic element, a memory element or the like, are stacked via an adhesive or the like and each element is bonded electrically in order to exhibit functions more efficiently. In this case, in order to avoid increase of thickness of the package due to stacking, the thickness of the semiconductor element itself to be used for the stacked element may be designed to be thin, for example below 200 μm, in many cases. Thereby, the semiconductor element (chip) itself becomes fragile. Also, coupled with downsizing of the package, a ratio of chip area of the semiconductor element bonded directly on a substrate with respect to substrate area, wherein the semiconductor element is mounted, increases. Thereby, it causes increase of stress imparted on the semiconductor element bonded directly on the substrate. Further, since the semiconductor element has the above-mentioned stacked structure, there are a lot of interfaces. Due to such reasons, it has been difficult to maintain or improve reliability of the stacked package as a whole.